1. Field
The present disclosure relates to a method and apparatus for laying out decoupling cells (capacitors) in a semiconductor device.
2. Description of the Related Art
The enlargement of semiconductor devices has resulted in an increase in the number of simultaneously operated elements. Such simultaneous operation may cause fluctuation in the power supply voltage in a semiconductor device. Furthermore, operation errors may be caused by power supply noise or timing deviations. Therefore, to reduce power supply noise, decoupling cells (capacitors) are laid out between a low-voltage power supply wiring and a high-voltage power supply wiring of a semiconductor device. In a semiconductor device provided with such decoupling cells, the decoupling cells must be efficiently laid out to reduce the designing time.
When designing a semiconductor device, power supply noise (DvD) analysis is performed using an electronic design automation (EDA) tool to determine the dynamic fluctuation of the power supply voltage and lay out decoupling cells so as to reduce the amount of noise. The amount of noise is determined from the power supply noise analysis. However, the criterion is unclear for the determination of the amount of noise with respect to the positions for laying out the decoupling cells and the capacitance of the decoupling cells. Thus, the power supply noise analysis is repeated on corrected layout data after the decoupling cells have been laid out. That is, an optimized decoupling cell layout is determined through a trial and error method. Since this method requires a considerable time to determine the layout of decoupling cells, it is not suitable for highly integrated semiconductor devices. Furthermore, this method does not eliminate operation errors resulting from timing deviations caused by power supply noise.
In order to solve this problem, a signal path (hereinafter, simply referred to as path) that is believed to have been affected by a power supply fluctuation is extracted, and a simulation of operation for the semiconductor device is performed with a circuit simulator such as a simulation program with integrated circuit emphasis (Spice) simulator. The simulation result is used to determine whether or not timing requirements are satisfied. A decoupling cell is added near the path when the timing requirements are not satisfied. Then, the power supply noise analysis is performed again on the corrected layout data after the addition.